feat: I2C drivers
This commit is contained in:
@@ -1,7 +1,7 @@
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FetchContent_Declare(
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pyincp
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GIT_REPOSITORY git@repo.dsi.tecnico.ulisboa.pt:nanosatlab/istsat-2/incp.git
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GIT_TAG temp/CMake-integration
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GIT_TAG feat/cli-rework
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)
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FetchContent_MakeAvailable(pyincp)
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31
app/src/circular_buffer.h
Normal file
31
app/src/circular_buffer.h
Normal file
@@ -0,0 +1,31 @@
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#ifndef _CIRCULAR_BUFF_H_
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#define _CIRCULAR_BUFF_H_
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#include <stdbool.h>
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#define _CB_COUNT(buffer) (sizeof((buffer)->buf) / sizeof((buffer)->buf[0]))
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#define _CB_WRAP(buffer, idx) ((idx) % (_CB_COUNT(buffer)))
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#define CIRCULAR_BUFFER_ALL(name, type, capacity) \
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typedef struct { \
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volatile uint32_t tail, count; \
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volatile type buf[capacity]; \
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} name##_t; \
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void name##_init(volatile name##_t *buffer) { buffer->tail = buffer->count = 0; } \
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bool name##_append(volatile name##_t *buffer, type element) { if (buffer->count == _CB_COUNT(buffer)) return false; buffer->buf[_CB_WRAP(buffer, buffer->tail + buffer->count)] = element; ++buffer->count; return true; } \
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bool name##_append_range(volatile name##_t *buffer, type *elements, int count) { \
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for (int i = 0; i < count; ++i) \
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if (!name##_append(buffer, elements[i])) return false; \
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return true; \
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} \
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int name##_take(volatile name##_t *buffer, type *dest, uint32_t count) { \
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count = count > buffer->count ? buffer->count : count; \
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for (uint32_t i = 0; i < count; ++i) { \
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dest[i] = buffer->buf[_CB_WRAP(buffer, buffer->tail)]; \
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++buffer->tail; --buffer->count; \
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} \
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return count; \
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} \
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#endif
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@@ -1,7 +1,87 @@
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#include "main.h"
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#include "i2c.h"
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#include "stm32f411xe.h"
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#include "stm32f4xx_hal.h"
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#include "stm32f4xx_hal_gpio.h"
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#include "stm32f4xx_ll_i2c.h"
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#include "gen_wrapper.h"
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#include "circular_buffer.h"
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#define CIRC_BUF_SIZE (2*1024)
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CIRCULAR_BUFFER_ALL(circ_buff, uint8_t, CIRC_BUF_SIZE)
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static volatile circ_buff_t i2c_buf;
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void I2C1_EV_IRQHandler()
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{
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if (!LL_I2C_IsActiveFlag_ADDR(I2C1))
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Error_Handler();
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//Skip checking matched addr (should only be one)
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//Skip checking if receiving or transmitting (should always be false)
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LL_I2C_ClearFlag_ADDR(I2C1);
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//Allow buffer to grow until full
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while (i2c_buf.count < _CB_COUNT(&i2c_buf))
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{
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//Wait for data or stop flag
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while (!LL_I2C_IsActiveFlag_STOP(I2C1) && !LL_I2C_IsActiveFlag_RXNE(I2C1));
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if (LL_I2C_IsActiveFlag_STOP(I2C1))
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{
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LL_I2C_ClearFlag_STOP(I2C1);
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break;
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}
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else //Data received
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{
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uint8_t data = LL_I2C_ReceiveData8(I2C1);
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circ_buff_append_range(&i2c_buf, &data, 1);
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}
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}
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//Overflow or stop condition reached
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if (i2c_buf.count >= _CB_COUNT(&i2c_buf))
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Error_Handler();
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}
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bool I2C1_transmit_master(uint8_t addr, uint8_t *buf, uint8_t count)
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{
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while (LL_I2C_IsActiveFlag_BUSY(I2C1));
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//Transmit start
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LL_I2C_GenerateStartCondition(I2C1);
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while (!LL_I2C_IsActiveFlag_SB(I2C1));
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//Transmit address + write
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LL_I2C_TransmitData8(I2C1, addr << 1);
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while (!LL_I2C_IsActiveFlag_ADDR(I2C1));
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LL_I2C_ClearFlag_ADDR(I2C1);
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for (int i = 0; i < count; ++i)
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{
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while (!LL_I2C_IsActiveFlag_TXE(I2C1));
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if (LL_I2C_IsActiveFlag_AF(I2C1))
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{
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//REVIEW: Anything else neeeded?
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LL_I2C_Disable(I2C1);
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LL_I2C_Enable(I2C1);
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return false;
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}
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LL_I2C_TransmitData8(I2C1, buf[i]);
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}
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LL_I2C_GenerateStopCondition(I2C1);
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while (LL_I2C_IsActiveFlag_STOP(I2C1));
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LL_I2C_Disable(I2C1);
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LL_I2C_Enable(I2C1);
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return true;
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}
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int my_main()
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{
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@@ -32,8 +32,6 @@ extern "C" {
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/* USER CODE END Includes */
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extern I2C_HandleTypeDef hi2c1;
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/* USER CODE BEGIN Private defines */
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/* USER CODE END Private defines */
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@@ -29,6 +29,18 @@ extern "C" {
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hal.h"
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#include "stm32f4xx_ll_i2c.h"
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#include "stm32f4xx_ll_bus.h"
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#include "stm32f4xx_ll_cortex.h"
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#include "stm32f4xx_ll_rcc.h"
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#include "stm32f4xx_ll_system.h"
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#include "stm32f4xx_ll_utils.h"
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#include "stm32f4xx_ll_pwr.h"
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#include "stm32f4xx_ll_gpio.h"
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#include "stm32f4xx_ll_dma.h"
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#include "stm32f4xx_ll_exti.h"
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/* Private includes ----------------------------------------------------------*/
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/* USER CODE BEGIN Includes */
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53
cubemx/Core/Inc/stm32_assert.h
Normal file
53
cubemx/Core/Inc/stm32_assert.h
Normal file
@@ -0,0 +1,53 @@
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/* USER CODE BEGIN Header */
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/**
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******************************************************************************
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* @file stm32_assert.h
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* @author MCD Application Team
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* @brief STM32 assert file.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2018 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* USER CODE END Header */
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32_ASSERT_H
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#define __STM32_ASSERT_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/* Includes ------------------------------------------------------------------*/
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/* Exported macro ------------------------------------------------------------*/
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#ifdef USE_FULL_ASSERT
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/**
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* @brief The assert_param macro is used for function's parameters check.
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* @param expr If expr is false, it calls assert_failed function
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* which reports the name of the source file and the source
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* line number of the call that failed.
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* If expr is true, it returns no value.
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* @retval None
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*/
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#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
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/* Exported functions ------------------------------------------------------- */
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void assert_failed(uint8_t *file, uint32_t line);
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#else
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#define assert_param(expr) ((void)0U)
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#endif /* USE_FULL_ASSERT */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __STM32_ASSERT_H */
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@@ -53,7 +53,7 @@
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/* #define HAL_SRAM_MODULE_ENABLED */
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/* #define HAL_SDRAM_MODULE_ENABLED */
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/* #define HAL_HASH_MODULE_ENABLED */
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#define HAL_I2C_MODULE_ENABLED
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/* #define HAL_I2C_MODULE_ENABLED */
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/* #define HAL_I2S_MODULE_ENABLED */
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/* #define HAL_IWDG_MODULE_ENABLED */
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/* #define HAL_LTDC_MODULE_ENABLED */
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@@ -24,8 +24,6 @@
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/* USER CODE END 0 */
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I2C_HandleTypeDef hi2c1;
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/* I2C1 init function */
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void MX_I2C1_Init(void)
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{
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@@ -34,83 +32,49 @@ void MX_I2C1_Init(void)
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/* USER CODE END I2C1_Init 0 */
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LL_I2C_InitTypeDef I2C_InitStruct = {0};
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LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOB);
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/**I2C1 GPIO Configuration
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PB8 ------> I2C1_SCL
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PB9 ------> I2C1_SDA
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*/
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GPIO_InitStruct.Pin = LL_GPIO_PIN_8|LL_GPIO_PIN_9;
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GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
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GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_OPENDRAIN;
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GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
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GPIO_InitStruct.Alternate = LL_GPIO_AF_4;
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LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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/* Peripheral clock enable */
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1);
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/* USER CODE BEGIN I2C1_Init 1 */
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/* USER CODE END I2C1_Init 1 */
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hi2c1.Instance = I2C1;
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hi2c1.Init.ClockSpeed = 100000;
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hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
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hi2c1.Init.OwnAddress1 = 0;
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hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
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hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
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hi2c1.Init.OwnAddress2 = 0;
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hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
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hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
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if (HAL_I2C_Init(&hi2c1) != HAL_OK)
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{
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Error_Handler();
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}
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/** I2C Initialization
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*/
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LL_I2C_DisableOwnAddress2(I2C1);
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LL_I2C_DisableGeneralCall(I2C1);
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LL_I2C_EnableClockStretching(I2C1);
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I2C_InitStruct.PeripheralMode = LL_I2C_MODE_I2C;
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I2C_InitStruct.ClockSpeed = 100000;
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I2C_InitStruct.DutyCycle = LL_I2C_DUTYCYCLE_2;
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I2C_InitStruct.OwnAddress1 = 0;
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I2C_InitStruct.TypeAcknowledge = LL_I2C_ACK;
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I2C_InitStruct.OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT;
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LL_I2C_Init(I2C1, &I2C_InitStruct);
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LL_I2C_SetOwnAddress2(I2C1, 0);
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/* USER CODE BEGIN I2C1_Init 2 */
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/* USER CODE END I2C1_Init 2 */
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}
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void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle)
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{
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GPIO_InitTypeDef GPIO_InitStruct = {0};
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if(i2cHandle->Instance==I2C1)
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{
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/* USER CODE BEGIN I2C1_MspInit 0 */
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/* USER CODE END I2C1_MspInit 0 */
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__HAL_RCC_GPIOB_CLK_ENABLE();
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/**I2C1 GPIO Configuration
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PB8 ------> I2C1_SCL
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PB9 ------> I2C1_SDA
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*/
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GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
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HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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/* I2C1 clock enable */
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__HAL_RCC_I2C1_CLK_ENABLE();
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/* USER CODE BEGIN I2C1_MspInit 1 */
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/* USER CODE END I2C1_MspInit 1 */
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}
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}
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void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle)
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{
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if(i2cHandle->Instance==I2C1)
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{
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/* USER CODE BEGIN I2C1_MspDeInit 0 */
|
||||
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||||
/* USER CODE END I2C1_MspDeInit 0 */
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/* Peripheral clock disable */
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__HAL_RCC_I2C1_CLK_DISABLE();
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/**I2C1 GPIO Configuration
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PB8 ------> I2C1_SCL
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PB9 ------> I2C1_SDA
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||||
*/
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HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_9);
|
||||
|
||||
/* USER CODE BEGIN I2C1_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END I2C1_MspDeInit 1 */
|
||||
}
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
|
||||
@@ -1,741 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2C HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_HAL_I2C_H
|
||||
#define __STM32F4xx_HAL_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Exported_Types I2C Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
|
||||
* @brief I2C Configuration Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockSpeed; /*!< Specifies the clock frequency.
|
||||
This parameter must be set to a value lower than 400kHz */
|
||||
|
||||
uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
|
||||
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_addressing_mode */
|
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_dual_addressing_mode */
|
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref I2C_general_call_addressing_mode */
|
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref I2C_nostretch_mode */
|
||||
|
||||
} I2C_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_state_structure_definition HAL state structure definition
|
||||
* @brief HAL State structure definition
|
||||
* @note HAL I2C State value coding follow below described bitmap :
|
||||
* b7-b6 Error information
|
||||
* 00 : No Error
|
||||
* 01 : Abort (Abort user request on going)
|
||||
* 10 : Timeout
|
||||
* 11 : Error
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral initialized and ready to use. HAL I2C Init function called)
|
||||
* b4 (not used)
|
||||
* x : Should be set to 0
|
||||
* b3
|
||||
* 0 : Ready or Busy (No Listen mode ongoing)
|
||||
* 1 : Listen (Peripheral in Address Listen Mode)
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (Peripheral busy with some configuration or internal operations)
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
|
||||
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
|
||||
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
|
||||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
|
||||
|
||||
} HAL_I2C_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
|
||||
* @brief HAL Mode structure definition
|
||||
* @note HAL I2C Mode value coding follow below described bitmap :\n
|
||||
* b7 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b6\n
|
||||
* 0 : None\n
|
||||
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
|
||||
* b5\n
|
||||
* 0 : None\n
|
||||
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
|
||||
* b4\n
|
||||
* 0 : None\n
|
||||
* 1 : Master (HAL I2C communication is in Master Mode)\n
|
||||
* b3-b2-b1-b0 (not used)\n
|
||||
* xxxx : Should be set to 0000
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
|
||||
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
|
||||
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
|
||||
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
|
||||
|
||||
} HAL_I2C_ModeTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
|
||||
* @brief I2C Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */
|
||||
#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */
|
||||
#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */
|
||||
#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */
|
||||
#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */
|
||||
#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */
|
||||
#define HAL_I2C_ERROR_SIZE 0x00000040U /*!< Size Management error */
|
||||
#define HAL_I2C_ERROR_DMA_PARAM 0x00000080U /*!< DMA Parameter Error */
|
||||
#define HAL_I2C_WRONG_START 0x00000200U /*!< Wrong start Error */
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_I2C_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
|
||||
* @brief I2C handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __I2C_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< I2C registers base address */
|
||||
|
||||
I2C_InitTypeDef Init; /*!< I2C communication parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
|
||||
|
||||
uint16_t XferSize; /*!< I2C transfer size */
|
||||
|
||||
__IO uint16_t XferCount; /*!< I2C transfer counter */
|
||||
|
||||
__IO uint32_t XferOptions; /*!< I2C transfer options */
|
||||
|
||||
__IO uint32_t PreviousState; /*!< I2C communication Previous state and mode
|
||||
context for internal usage */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
||||
|
||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
||||
|
||||
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< I2C Error code */
|
||||
|
||||
__IO uint32_t Devaddress; /*!< I2C Target device address */
|
||||
|
||||
__IO uint32_t Memaddress; /*!< I2C Target memory address */
|
||||
|
||||
__IO uint32_t MemaddSize; /*!< I2C Target memory address size */
|
||||
|
||||
__IO uint32_t EventCount; /*!< I2C Event counter */
|
||||
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */
|
||||
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */
|
||||
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */
|
||||
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */
|
||||
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */
|
||||
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */
|
||||
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */
|
||||
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */
|
||||
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */
|
||||
|
||||
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */
|
||||
|
||||
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
} I2C_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL I2C Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
|
||||
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
|
||||
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
|
||||
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
|
||||
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
|
||||
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
|
||||
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
|
||||
|
||||
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
|
||||
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
|
||||
|
||||
} HAL_I2C_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL I2C Callback pointer definition
|
||||
*/
|
||||
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
|
||||
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Constants I2C Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DUTYCYCLE_2 0x00000000U
|
||||
#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_addressing_mode I2C addressing mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ADDRESSINGMODE_7BIT 0x00004000U
|
||||
#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DUALADDRESS_DISABLE 0x00000000U
|
||||
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_GENERALCALL_DISABLE 0x00000000U
|
||||
#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_nostretch_mode I2C nostretch mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NOSTRETCH_DISABLE 0x00000000U
|
||||
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
|
||||
* @{
|
||||
*/
|
||||
#define I2C_MEMADD_SIZE_8BIT 0x00000001U
|
||||
#define I2C_MEMADD_SIZE_16BIT 0x00000010U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DIRECTION_RECEIVE 0x00000000U
|
||||
#define I2C_DIRECTION_TRANSMIT 0x00000001U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FIRST_FRAME 0x00000001U
|
||||
#define I2C_FIRST_AND_NEXT_FRAME 0x00000002U
|
||||
#define I2C_NEXT_FRAME 0x00000004U
|
||||
#define I2C_FIRST_AND_LAST_FRAME 0x00000008U
|
||||
#define I2C_LAST_FRAME_NO_STOP 0x00000010U
|
||||
#define I2C_LAST_FRAME 0x00000020U
|
||||
|
||||
/* List of XferOptions in usage of :
|
||||
* 1- Restart condition in all use cases (direction change or not)
|
||||
*/
|
||||
#define I2C_OTHER_FRAME (0x00AA0000U)
|
||||
#define I2C_OTHER_AND_LAST_FRAME (0xAA000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
|
||||
* @brief I2C Interrupt definition
|
||||
* Elements values convention: 0xXXXXXXXX
|
||||
* - XXXXXXXX : Interrupt control mask
|
||||
* @{
|
||||
*/
|
||||
#define I2C_IT_BUF I2C_CR2_ITBUFEN
|
||||
#define I2C_IT_EVT I2C_CR2_ITEVTEN
|
||||
#define I2C_IT_ERR I2C_CR2_ITERREN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Flag_definition I2C Flag definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_FLAG_OVR 0x00010800U
|
||||
#define I2C_FLAG_AF 0x00010400U
|
||||
#define I2C_FLAG_ARLO 0x00010200U
|
||||
#define I2C_FLAG_BERR 0x00010100U
|
||||
#define I2C_FLAG_TXE 0x00010080U
|
||||
#define I2C_FLAG_RXNE 0x00010040U
|
||||
#define I2C_FLAG_STOPF 0x00010010U
|
||||
#define I2C_FLAG_ADD10 0x00010008U
|
||||
#define I2C_FLAG_BTF 0x00010004U
|
||||
#define I2C_FLAG_ADDR 0x00010002U
|
||||
#define I2C_FLAG_SB 0x00010001U
|
||||
#define I2C_FLAG_DUALF 0x00100080U
|
||||
#define I2C_FLAG_GENCALL 0x00100010U
|
||||
#define I2C_FLAG_TRA 0x00100004U
|
||||
#define I2C_FLAG_BUSY 0x00100002U
|
||||
#define I2C_FLAG_MSL 0x00100001U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Macros I2C Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset I2C handle state.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
|
||||
#endif
|
||||
|
||||
/** @brief Enable or disable the specified I2C interrupts.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2C_IT_BUF: Buffer interrupt enable
|
||||
* @arg I2C_IT_EVT: Event interrupt enable
|
||||
* @arg I2C_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))
|
||||
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
|
||||
|
||||
/** @brief Checks if the specified I2C interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2C_IT_BUF: Buffer interrupt enable
|
||||
* @arg I2C_IT_EVT: Event interrupt enable
|
||||
* @arg I2C_IT_ERR: Error interrupt enable
|
||||
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks whether the specified I2C flag is set or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2C_FLAG_OVR: Overrun/Underrun flag
|
||||
* @arg I2C_FLAG_AF: Acknowledge failure flag
|
||||
* @arg I2C_FLAG_ARLO: Arbitration lost flag
|
||||
* @arg I2C_FLAG_BERR: Bus error flag
|
||||
* @arg I2C_FLAG_TXE: Data register empty flag
|
||||
* @arg I2C_FLAG_RXNE: Data register not empty flag
|
||||
* @arg I2C_FLAG_STOPF: Stop detection flag
|
||||
* @arg I2C_FLAG_ADD10: 10-bit header sent flag
|
||||
* @arg I2C_FLAG_BTF: Byte transfer finished flag
|
||||
* @arg I2C_FLAG_ADDR: Address sent flag
|
||||
* Address matched flag
|
||||
* @arg I2C_FLAG_SB: Start bit flag
|
||||
* @arg I2C_FLAG_DUALF: Dual flag
|
||||
* @arg I2C_FLAG_GENCALL: General call header flag
|
||||
* @arg I2C_FLAG_TRA: Transmitter/Receiver flag
|
||||
* @arg I2C_FLAG_BUSY: Bus busy flag
|
||||
* @arg I2C_FLAG_MSL: Master/Slave flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? \
|
||||
(((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) : \
|
||||
(((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET))
|
||||
|
||||
/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
|
||||
* @arg I2C_FLAG_AF: Acknowledge failure flag
|
||||
* @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
|
||||
* @arg I2C_FLAG_BERR: Bus error flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
|
||||
|
||||
/** @brief Clears the I2C ADDR pending flag.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
tmpreg = (__HANDLE__)->Instance->SR1; \
|
||||
tmpreg = (__HANDLE__)->Instance->SR2; \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Clears the I2C STOPF pending flag.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
tmpreg = (__HANDLE__)->Instance->SR1; \
|
||||
SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Enable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
|
||||
|
||||
/** @brief Disable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include I2C HAL Extension module */
|
||||
#include "stm32f4xx_hal_i2c_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2C_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions******************************/
|
||||
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions ****************************************************/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
|
||||
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
|
||||
|
||||
/******* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State, Mode and Error functions *********************************/
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Constants I2C Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FLAG_MASK 0x0000FFFFU
|
||||
#define I2C_MIN_PCLK_FREQ_STANDARD 2000000U /*!< 2 MHz */
|
||||
#define I2C_MIN_PCLK_FREQ_FAST 4000000U /*!< 4 MHz */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Macros I2C Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST))
|
||||
#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__) (((((__PCLK__) - 1U)/((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR)
|
||||
#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U)
|
||||
#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
|
||||
#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U)? 4U:I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))
|
||||
#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
|
||||
#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
|
||||
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
|
||||
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
|
||||
|
||||
#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (uint8_t)(~I2C_OAR1_ADD0)))
|
||||
#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
|
||||
|
||||
#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
|
||||
#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0)))
|
||||
#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1))))
|
||||
|
||||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8)))
|
||||
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
|
||||
|
||||
/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
|
||||
((CYCLE) == I2C_DUTYCYCLE_16_9))
|
||||
#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
|
||||
((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
|
||||
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
|
||||
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
|
||||
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
|
||||
((CALL) == I2C_GENERALCALL_ENABLE))
|
||||
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
|
||||
((STRETCH) == I2C_NOSTRETCH_ENABLE))
|
||||
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
|
||||
((SIZE) == I2C_MEMADD_SIZE_16BIT))
|
||||
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U))
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U)
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U)
|
||||
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
|
||||
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
|
||||
|
||||
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
|
||||
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
|
||||
|
||||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
|
||||
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Functions I2C Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F4xx_HAL_I2C_H */
|
||||
|
||||
@@ -1,115 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_i2c_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2C HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_HAL_I2C_EX_H
|
||||
#define __STM32F4xx_HAL_I2C_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Exported_Constants I2C Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Analog_Filter I2C Analog Filter
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
|
||||
#define I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2CEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Constants I2C Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Macros I2C Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
|
||||
((FILTER) == I2C_ANALOGFILTER_DISABLE))
|
||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_HAL_I2C_EX_H */
|
||||
|
||||
|
||||
@@ -8,8 +8,6 @@ target_sources(cubemx PRIVATE
|
||||
stm32f4xx_hal_flash_ex.c
|
||||
stm32f4xx_hal_flash_ramfunc.c
|
||||
stm32f4xx_hal_gpio.c
|
||||
stm32f4xx_hal_i2c.c
|
||||
stm32f4xx_hal_i2c_ex.c
|
||||
stm32f4xx_hal_pwr.c
|
||||
stm32f4xx_hal_pwr_ex.c
|
||||
stm32f4xx_hal_rcc.c
|
||||
@@ -17,4 +15,10 @@ target_sources(cubemx PRIVATE
|
||||
stm32f4xx_hal_tim.c
|
||||
stm32f4xx_hal_tim_ex.c
|
||||
stm32f4xx_hal_uart.c
|
||||
stm32f4xx_ll_dma.c
|
||||
stm32f4xx_ll_exti.c
|
||||
stm32f4xx_ll_gpio.c
|
||||
stm32f4xx_ll_i2c.c
|
||||
stm32f4xx_ll_rcc.c
|
||||
stm32f4xx_ll_utils.c
|
||||
)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,182 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_i2c_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief I2C Extension HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of I2C extension peripheral:
|
||||
* + Extension features functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### I2C peripheral extension features #####
|
||||
==============================================================================
|
||||
|
||||
[..] Comparing to other previous devices, the I2C interface for STM32F427xx/437xx/
|
||||
429xx/439xx devices contains the following additional features :
|
||||
|
||||
(+) Possibility to disable or enable Analog Noise Filter
|
||||
(+) Use of a configured Digital Noise Filter
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..] This driver provides functions to configure Noise Filter
|
||||
(#) Configure I2C Analog noise filter using the function HAL_I2C_AnalogFilter_Config()
|
||||
(#) Configure I2C Digital noise filter using the function HAL_I2C_DigitalFilter_Config()
|
||||
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx I2CEx
|
||||
* @brief I2C HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
|
||||
#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Exported_Functions I2C Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions_Group1 Extension features functions
|
||||
* @brief Extension features functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extension features functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure Noise Filters
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures I2C Analog noise filter.
|
||||
* @param hi2c pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @param AnalogFilter new state of the Analog filter.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Reset I2Cx ANOFF bit */
|
||||
hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF);
|
||||
|
||||
/* Disable the analog filter */
|
||||
hi2c->Instance->FLTR |= AnalogFilter;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures I2C Digital noise filter.
|
||||
* @param hi2c pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
|
||||
{
|
||||
uint16_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Get the old register value */
|
||||
tmpreg = hi2c->Instance->FLTR;
|
||||
|
||||
/* Reset I2Cx DNF bit [3:0] */
|
||||
tmpreg &= ~(I2C_FLTR_DNF);
|
||||
|
||||
/* Set I2Cx DNF coefficient */
|
||||
tmpreg |= DigitalFilter;
|
||||
|
||||
/* Store the new register value */
|
||||
hi2c->Instance->FLTR = tmpreg;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
423
cubemx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dma.c
Normal file
423
cubemx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dma.c
Normal file
@@ -0,0 +1,423 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_ll_dma.c
|
||||
* @author MCD Application Team
|
||||
* @brief DMA LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_ll_dma.h"
|
||||
#include "stm32f4xx_ll_bus.h"
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F4xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (DMA1) || defined (DMA2)
|
||||
|
||||
/** @defgroup DMA_LL DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup DMA_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
|
||||
((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
|
||||
((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
|
||||
|
||||
#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
|
||||
((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \
|
||||
((__VALUE__) == LL_DMA_MODE_PFCTRL))
|
||||
|
||||
#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
|
||||
((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
|
||||
|
||||
#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
|
||||
((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
|
||||
|
||||
#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
|
||||
((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
|
||||
((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
|
||||
|
||||
#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
|
||||
((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
|
||||
((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
|
||||
|
||||
#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
|
||||
|
||||
#define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \
|
||||
((__VALUE__) == LL_DMA_CHANNEL_1) || \
|
||||
((__VALUE__) == LL_DMA_CHANNEL_2) || \
|
||||
((__VALUE__) == LL_DMA_CHANNEL_3) || \
|
||||
((__VALUE__) == LL_DMA_CHANNEL_4) || \
|
||||
((__VALUE__) == LL_DMA_CHANNEL_5) || \
|
||||
((__VALUE__) == LL_DMA_CHANNEL_6) || \
|
||||
((__VALUE__) == LL_DMA_CHANNEL_7))
|
||||
|
||||
#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
|
||||
((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
|
||||
((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
|
||||
((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
|
||||
|
||||
#define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \
|
||||
(((STREAM) == LL_DMA_STREAM_0) || \
|
||||
((STREAM) == LL_DMA_STREAM_1) || \
|
||||
((STREAM) == LL_DMA_STREAM_2) || \
|
||||
((STREAM) == LL_DMA_STREAM_3) || \
|
||||
((STREAM) == LL_DMA_STREAM_4) || \
|
||||
((STREAM) == LL_DMA_STREAM_5) || \
|
||||
((STREAM) == LL_DMA_STREAM_6) || \
|
||||
((STREAM) == LL_DMA_STREAM_7) || \
|
||||
((STREAM) == LL_DMA_STREAM_ALL))) ||\
|
||||
(((INSTANCE) == DMA2) && \
|
||||
(((STREAM) == LL_DMA_STREAM_0) || \
|
||||
((STREAM) == LL_DMA_STREAM_1) || \
|
||||
((STREAM) == LL_DMA_STREAM_2) || \
|
||||
((STREAM) == LL_DMA_STREAM_3) || \
|
||||
((STREAM) == LL_DMA_STREAM_4) || \
|
||||
((STREAM) == LL_DMA_STREAM_5) || \
|
||||
((STREAM) == LL_DMA_STREAM_6) || \
|
||||
((STREAM) == LL_DMA_STREAM_7) || \
|
||||
((STREAM) == LL_DMA_STREAM_ALL))))
|
||||
|
||||
#define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
|
||||
((STATE) == LL_DMA_FIFOMODE_ENABLE))
|
||||
|
||||
#define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \
|
||||
((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \
|
||||
((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \
|
||||
((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
|
||||
|
||||
#define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \
|
||||
((BURST) == LL_DMA_MBURST_INC4) || \
|
||||
((BURST) == LL_DMA_MBURST_INC8) || \
|
||||
((BURST) == LL_DMA_MBURST_INC16))
|
||||
|
||||
#define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \
|
||||
((BURST) == LL_DMA_PBURST_INC4) || \
|
||||
((BURST) == LL_DMA_PBURST_INC8) || \
|
||||
((BURST) == LL_DMA_PBURST_INC16))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DMA_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initialize the DMA registers to their default reset values.
|
||||
* @param DMAx DMAx Instance
|
||||
* @param Stream This parameter can be one of the following values:
|
||||
* @arg @ref LL_DMA_STREAM_0
|
||||
* @arg @ref LL_DMA_STREAM_1
|
||||
* @arg @ref LL_DMA_STREAM_2
|
||||
* @arg @ref LL_DMA_STREAM_3
|
||||
* @arg @ref LL_DMA_STREAM_4
|
||||
* @arg @ref LL_DMA_STREAM_5
|
||||
* @arg @ref LL_DMA_STREAM_6
|
||||
* @arg @ref LL_DMA_STREAM_7
|
||||
* @arg @ref LL_DMA_STREAM_ALL
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: DMA registers are de-initialized
|
||||
* - ERROR: DMA registers are not de-initialized
|
||||
*/
|
||||
uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
|
||||
{
|
||||
DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0;
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check the DMA Instance DMAx and Stream parameters*/
|
||||
assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
|
||||
|
||||
if (Stream == LL_DMA_STREAM_ALL)
|
||||
{
|
||||
if (DMAx == DMA1)
|
||||
{
|
||||
/* Force reset of DMA clock */
|
||||
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
|
||||
|
||||
/* Release reset of DMA clock */
|
||||
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
|
||||
}
|
||||
else if (DMAx == DMA2)
|
||||
{
|
||||
/* Force reset of DMA clock */
|
||||
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
|
||||
|
||||
/* Release reset of DMA clock */
|
||||
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
|
||||
}
|
||||
else
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected Stream */
|
||||
LL_DMA_DisableStream(DMAx,Stream);
|
||||
|
||||
/* Get the DMA Stream Instance */
|
||||
tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
|
||||
|
||||
/* Reset DMAx_Streamy configuration register */
|
||||
LL_DMA_WriteReg(tmp, CR, 0U);
|
||||
|
||||
/* Reset DMAx_Streamy remaining bytes register */
|
||||
LL_DMA_WriteReg(tmp, NDTR, 0U);
|
||||
|
||||
/* Reset DMAx_Streamy peripheral address register */
|
||||
LL_DMA_WriteReg(tmp, PAR, 0U);
|
||||
|
||||
/* Reset DMAx_Streamy memory address register */
|
||||
LL_DMA_WriteReg(tmp, M0AR, 0U);
|
||||
|
||||
/* Reset DMAx_Streamy memory address register */
|
||||
LL_DMA_WriteReg(tmp, M1AR, 0U);
|
||||
|
||||
/* Reset DMAx_Streamy FIFO control register */
|
||||
LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
|
||||
|
||||
/* Reset Channel register field for DMAx Stream*/
|
||||
LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0);
|
||||
|
||||
if(Stream == LL_DMA_STREAM_0)
|
||||
{
|
||||
/* Reset the Stream0 pending flags */
|
||||
DMAx->LIFCR = 0x0000003FU;
|
||||
}
|
||||
else if(Stream == LL_DMA_STREAM_1)
|
||||
{
|
||||
/* Reset the Stream1 pending flags */
|
||||
DMAx->LIFCR = 0x00000F40U;
|
||||
}
|
||||
else if(Stream == LL_DMA_STREAM_2)
|
||||
{
|
||||
/* Reset the Stream2 pending flags */
|
||||
DMAx->LIFCR = 0x003F0000U;
|
||||
}
|
||||
else if(Stream == LL_DMA_STREAM_3)
|
||||
{
|
||||
/* Reset the Stream3 pending flags */
|
||||
DMAx->LIFCR = 0x0F400000U;
|
||||
}
|
||||
else if(Stream == LL_DMA_STREAM_4)
|
||||
{
|
||||
/* Reset the Stream4 pending flags */
|
||||
DMAx->HIFCR = 0x0000003FU;
|
||||
}
|
||||
else if(Stream == LL_DMA_STREAM_5)
|
||||
{
|
||||
/* Reset the Stream5 pending flags */
|
||||
DMAx->HIFCR = 0x00000F40U;
|
||||
}
|
||||
else if(Stream == LL_DMA_STREAM_6)
|
||||
{
|
||||
/* Reset the Stream6 pending flags */
|
||||
DMAx->HIFCR = 0x003F0000U;
|
||||
}
|
||||
else if(Stream == LL_DMA_STREAM_7)
|
||||
{
|
||||
/* Reset the Stream7 pending flags */
|
||||
DMAx->HIFCR = 0x0F400000U;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
|
||||
* @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
|
||||
* @arg @ref __LL_DMA_GET_INSTANCE
|
||||
* @arg @ref __LL_DMA_GET_STREAM
|
||||
* @param DMAx DMAx Instance
|
||||
* @param Stream This parameter can be one of the following values:
|
||||
* @arg @ref LL_DMA_STREAM_0
|
||||
* @arg @ref LL_DMA_STREAM_1
|
||||
* @arg @ref LL_DMA_STREAM_2
|
||||
* @arg @ref LL_DMA_STREAM_3
|
||||
* @arg @ref LL_DMA_STREAM_4
|
||||
* @arg @ref LL_DMA_STREAM_5
|
||||
* @arg @ref LL_DMA_STREAM_6
|
||||
* @arg @ref LL_DMA_STREAM_7
|
||||
* @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: DMA registers are initialized
|
||||
* - ERROR: Not applicable
|
||||
*/
|
||||
uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
|
||||
{
|
||||
/* Check the DMA Instance DMAx and Stream parameters*/
|
||||
assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
|
||||
|
||||
/* Check the DMA parameters from DMA_InitStruct */
|
||||
assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
|
||||
assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
|
||||
assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
|
||||
assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
|
||||
assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
|
||||
assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
|
||||
assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
|
||||
assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel));
|
||||
assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
|
||||
assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
|
||||
/* Check the memory burst, peripheral burst and FIFO threshold parameters only
|
||||
when FIFO mode is enabled */
|
||||
if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
|
||||
{
|
||||
assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
|
||||
assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
|
||||
assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
|
||||
}
|
||||
|
||||
/*---------------------------- DMAx SxCR Configuration ------------------------
|
||||
* Configure DMAx_Streamy: data transfer direction, data transfer mode,
|
||||
* peripheral and memory increment mode,
|
||||
* data size alignment and priority level with parameters :
|
||||
* - Direction: DMA_SxCR_DIR[1:0] bits
|
||||
* - Mode: DMA_SxCR_CIRC bit
|
||||
* - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit
|
||||
* - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit
|
||||
* - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
|
||||
* - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
|
||||
* - Priority: DMA_SxCR_PL[1:0] bits
|
||||
*/
|
||||
LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
|
||||
DMA_InitStruct->Mode | \
|
||||
DMA_InitStruct->PeriphOrM2MSrcIncMode | \
|
||||
DMA_InitStruct->MemoryOrM2MDstIncMode | \
|
||||
DMA_InitStruct->PeriphOrM2MSrcDataSize | \
|
||||
DMA_InitStruct->MemoryOrM2MDstDataSize | \
|
||||
DMA_InitStruct->Priority
|
||||
);
|
||||
|
||||
if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
|
||||
{
|
||||
/*---------------------------- DMAx SxFCR Configuration ------------------------
|
||||
* Configure DMAx_Streamy: fifo mode and fifo threshold with parameters :
|
||||
* - FIFOMode: DMA_SxFCR_DMDIS bit
|
||||
* - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits
|
||||
*/
|
||||
LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);
|
||||
|
||||
/*---------------------------- DMAx SxCR Configuration --------------------------
|
||||
* Configure DMAx_Streamy: memory burst transfer with parameters :
|
||||
* - MemBurst: DMA_SxCR_MBURST[1:0] bits
|
||||
*/
|
||||
LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst);
|
||||
|
||||
/*---------------------------- DMAx SxCR Configuration --------------------------
|
||||
* Configure DMAx_Streamy: peripheral burst transfer with parameters :
|
||||
* - PeriphBurst: DMA_SxCR_PBURST[1:0] bits
|
||||
*/
|
||||
LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst);
|
||||
}
|
||||
|
||||
/*-------------------------- DMAx SxM0AR Configuration --------------------------
|
||||
* Configure the memory or destination base address with parameter :
|
||||
* - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits
|
||||
*/
|
||||
LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
|
||||
|
||||
/*-------------------------- DMAx SxPAR Configuration ---------------------------
|
||||
* Configure the peripheral or source base address with parameter :
|
||||
* - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits
|
||||
*/
|
||||
LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
|
||||
|
||||
/*--------------------------- DMAx SxNDTR Configuration -------------------------
|
||||
* Configure the peripheral base address with parameter :
|
||||
* - NbData: DMA_SxNDT[15:0] bits
|
||||
*/
|
||||
LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
|
||||
|
||||
/*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
|
||||
* Configure the peripheral base address with parameter :
|
||||
* - PeriphRequest: DMA_SxCR_CHSEL[2:0] bits
|
||||
*/
|
||||
LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_DMA_InitTypeDef field to default value.
|
||||
* @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
|
||||
{
|
||||
/* Set DMA_InitStruct fields to default values */
|
||||
DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
|
||||
DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
|
||||
DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
|
||||
DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
|
||||
DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
|
||||
DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
|
||||
DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
|
||||
DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
|
||||
DMA_InitStruct->NbData = 0x00000000U;
|
||||
DMA_InitStruct->Channel = LL_DMA_CHANNEL_0;
|
||||
DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
|
||||
DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE;
|
||||
DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4;
|
||||
DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE;
|
||||
DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DMA1 || DMA2 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
212
cubemx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_exti.c
Normal file
212
cubemx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_exti.c
Normal file
@@ -0,0 +1,212 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_ll_exti.c
|
||||
* @author MCD Application Team
|
||||
* @brief EXTI LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_ll_exti.h"
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F4xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (EXTI)
|
||||
|
||||
/** @defgroup EXTI_LL EXTI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup EXTI_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
|
||||
|
||||
#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
|
||||
|| ((__VALUE__) == LL_EXTI_MODE_EVENT) \
|
||||
|| ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
|
||||
|
||||
|
||||
#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
|
||||
|| ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
|
||||
|| ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
|
||||
|| ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup EXTI_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initialize the EXTI registers to their default reset values.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: EXTI registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
uint32_t LL_EXTI_DeInit(void)
|
||||
{
|
||||
/* Interrupt mask register set to default reset values */
|
||||
LL_EXTI_WriteReg(IMR, 0x00000000U);
|
||||
/* Event mask register set to default reset values */
|
||||
LL_EXTI_WriteReg(EMR, 0x00000000U);
|
||||
/* Rising Trigger selection register set to default reset values */
|
||||
LL_EXTI_WriteReg(RTSR, 0x00000000U);
|
||||
/* Falling Trigger selection register set to default reset values */
|
||||
LL_EXTI_WriteReg(FTSR, 0x00000000U);
|
||||
/* Software interrupt event register set to default reset values */
|
||||
LL_EXTI_WriteReg(SWIER, 0x00000000U);
|
||||
/* Pending register set to default reset values */
|
||||
LL_EXTI_WriteReg(PR, 0x00FFFFFFU);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
|
||||
* @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: EXTI registers are initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
|
||||
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
|
||||
assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
|
||||
|
||||
/* ENABLE LineCommand */
|
||||
if (EXTI_InitStruct->LineCommand != DISABLE)
|
||||
{
|
||||
assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
|
||||
|
||||
/* Configure EXTI Lines in range from 0 to 31 */
|
||||
if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
|
||||
{
|
||||
switch (EXTI_InitStruct->Mode)
|
||||
{
|
||||
case LL_EXTI_MODE_IT:
|
||||
/* First Disable Event on provided Lines */
|
||||
LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
|
||||
/* Then Enable IT on provided Lines */
|
||||
LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
|
||||
break;
|
||||
case LL_EXTI_MODE_EVENT:
|
||||
/* First Disable IT on provided Lines */
|
||||
LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
|
||||
/* Then Enable Event on provided Lines */
|
||||
LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
|
||||
break;
|
||||
case LL_EXTI_MODE_IT_EVENT:
|
||||
/* Directly Enable IT & Event on provided Lines */
|
||||
LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
|
||||
LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
|
||||
break;
|
||||
default:
|
||||
status = ERROR;
|
||||
break;
|
||||
}
|
||||
if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
|
||||
{
|
||||
switch (EXTI_InitStruct->Trigger)
|
||||
{
|
||||
case LL_EXTI_TRIGGER_RISING:
|
||||
/* First Disable Falling Trigger on provided Lines */
|
||||
LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||
/* Then Enable Rising Trigger on provided Lines */
|
||||
LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||
break;
|
||||
case LL_EXTI_TRIGGER_FALLING:
|
||||
/* First Disable Rising Trigger on provided Lines */
|
||||
LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||
/* Then Enable Falling Trigger on provided Lines */
|
||||
LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||
break;
|
||||
case LL_EXTI_TRIGGER_RISING_FALLING:
|
||||
LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||
LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||
break;
|
||||
default:
|
||||
status = ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
/* DISABLE LineCommand */
|
||||
else
|
||||
{
|
||||
/* De-configure EXTI Lines in range from 0 to 31 */
|
||||
LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
|
||||
LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
|
||||
* @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
|
||||
{
|
||||
EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
|
||||
EXTI_InitStruct->LineCommand = DISABLE;
|
||||
EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
|
||||
EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined (EXTI) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
303
cubemx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_gpio.c
Normal file
303
cubemx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_gpio.c
Normal file
@@ -0,0 +1,303 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_ll_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @brief GPIO LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_ll_gpio.h"
|
||||
#include "stm32f4xx_ll_bus.h"
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F4xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
|
||||
|
||||
/** @addtogroup GPIO_LL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
|
||||
|
||||
#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
|
||||
((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
|
||||
((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
|
||||
((__VALUE__) == LL_GPIO_MODE_ANALOG))
|
||||
|
||||
#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\
|
||||
((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
|
||||
|
||||
#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\
|
||||
((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\
|
||||
((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\
|
||||
((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
|
||||
|
||||
#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\
|
||||
((__VALUE__) == LL_GPIO_PULL_UP) ||\
|
||||
((__VALUE__) == LL_GPIO_PULL_DOWN))
|
||||
|
||||
#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_1 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_2 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_3 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_4 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_5 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_6 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_7 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_8 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_9 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_10 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_11 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_12 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_13 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_14 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_15 ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initialize GPIO registers (Registers restored to their default values).
|
||||
* @param GPIOx GPIO Port
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: GPIO registers are de-initialized
|
||||
* - ERROR: Wrong GPIO Port
|
||||
*/
|
||||
ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
|
||||
/* Force and Release reset on clock of GPIOx Port */
|
||||
if (GPIOx == GPIOA)
|
||||
{
|
||||
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA);
|
||||
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA);
|
||||
}
|
||||
else if (GPIOx == GPIOB)
|
||||
{
|
||||
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB);
|
||||
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB);
|
||||
}
|
||||
else if (GPIOx == GPIOC)
|
||||
{
|
||||
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC);
|
||||
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC);
|
||||
}
|
||||
#if defined(GPIOD)
|
||||
else if (GPIOx == GPIOD)
|
||||
{
|
||||
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD);
|
||||
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD);
|
||||
}
|
||||
#endif /* GPIOD */
|
||||
#if defined(GPIOE)
|
||||
else if (GPIOx == GPIOE)
|
||||
{
|
||||
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE);
|
||||
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE);
|
||||
}
|
||||
#endif /* GPIOE */
|
||||
#if defined(GPIOF)
|
||||
else if (GPIOx == GPIOF)
|
||||
{
|
||||
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF);
|
||||
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF);
|
||||
}
|
||||
#endif /* GPIOF */
|
||||
#if defined(GPIOG)
|
||||
else if (GPIOx == GPIOG)
|
||||
{
|
||||
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOG);
|
||||
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOG);
|
||||
}
|
||||
#endif /* GPIOG */
|
||||
#if defined(GPIOH)
|
||||
else if (GPIOx == GPIOH)
|
||||
{
|
||||
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOH);
|
||||
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOH);
|
||||
}
|
||||
#endif /* GPIOH */
|
||||
#if defined(GPIOI)
|
||||
else if (GPIOx == GPIOI)
|
||||
{
|
||||
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOI);
|
||||
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOI);
|
||||
}
|
||||
#endif /* GPIOI */
|
||||
#if defined(GPIOJ)
|
||||
else if (GPIOx == GPIOJ)
|
||||
{
|
||||
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOJ);
|
||||
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOJ);
|
||||
}
|
||||
#endif /* GPIOJ */
|
||||
#if defined(GPIOK)
|
||||
else if (GPIOx == GPIOK)
|
||||
{
|
||||
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOK);
|
||||
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOK);
|
||||
}
|
||||
#endif /* GPIOK */
|
||||
else
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
|
||||
* @param GPIOx GPIO Port
|
||||
* @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
|
||||
* that contains the configuration information for the specified GPIO peripheral.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
|
||||
* - ERROR: Not applicable
|
||||
*/
|
||||
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
|
||||
{
|
||||
uint32_t pinpos = 0x00000000U;
|
||||
uint32_t currentpin = 0x00000000U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
|
||||
assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
|
||||
assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
|
||||
|
||||
/* ------------------------- Configure the port pins ---------------- */
|
||||
/* Initialize pinpos on first pin set */
|
||||
pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
|
||||
|
||||
/* Configure the port pins */
|
||||
while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
|
||||
{
|
||||
/* Get current io position */
|
||||
currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
|
||||
|
||||
if (currentpin)
|
||||
{
|
||||
|
||||
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
|
||||
{
|
||||
/* Check Speed mode parameters */
|
||||
assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
|
||||
|
||||
/* Speed mode configuration */
|
||||
LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
|
||||
|
||||
/* Check Output mode parameters */
|
||||
assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
|
||||
|
||||
/* Output mode configuration*/
|
||||
LL_GPIO_SetPinOutputType(GPIOx, currentpin, GPIO_InitStruct->OutputType);
|
||||
}
|
||||
|
||||
/* Pull-up Pull down resistor configuration*/
|
||||
LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
|
||||
|
||||
if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
|
||||
{
|
||||
/* Check Alternate parameter */
|
||||
assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
|
||||
|
||||
/* Speed mode configuration */
|
||||
if (POSITION_VAL(currentpin) < 0x00000008U)
|
||||
{
|
||||
LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
|
||||
}
|
||||
else
|
||||
{
|
||||
LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
|
||||
}
|
||||
}
|
||||
|
||||
/* Pin Mode configuration */
|
||||
LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
|
||||
}
|
||||
pinpos++;
|
||||
}
|
||||
|
||||
return (SUCCESS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
|
||||
* @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
|
||||
* whose fields will be set to default values.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
|
||||
{
|
||||
/* Reset GPIO init structure parameters values */
|
||||
GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL;
|
||||
GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG;
|
||||
GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
|
||||
GPIO_InitStruct->Pull = LL_GPIO_PULL_NO;
|
||||
GPIO_InitStruct->Alternate = LL_GPIO_AF_0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
251
cubemx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_i2c.c
Normal file
251
cubemx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_i2c.c
Normal file
@@ -0,0 +1,251 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_ll_i2c.c
|
||||
* @author MCD Application Team
|
||||
* @brief I2C LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_ll_i2c.h"
|
||||
#include "stm32f4xx_ll_bus.h"
|
||||
#include "stm32f4xx_ll_rcc.h"
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F4xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (I2C1) || defined (I2C2) || defined (I2C3)
|
||||
|
||||
/** @defgroup I2C_LL I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup I2C_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \
|
||||
((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \
|
||||
((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
|
||||
((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
|
||||
|
||||
#define IS_LL_I2C_CLOCK_SPEED(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST))
|
||||
|
||||
#define IS_LL_I2C_DUTY_CYCLE(__VALUE__) (((__VALUE__) == LL_I2C_DUTYCYCLE_2) || \
|
||||
((__VALUE__) == LL_I2C_DUTYCYCLE_16_9))
|
||||
|
||||
#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
|
||||
#define IS_LL_I2C_ANALOG_FILTER(__VALUE__) (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
|
||||
((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
|
||||
|
||||
#define IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
|
||||
|
||||
#endif
|
||||
#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
|
||||
|
||||
#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \
|
||||
((__VALUE__) == LL_I2C_NACK))
|
||||
|
||||
#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
|
||||
((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2C_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initialize the I2C registers to their default reset values.
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS I2C registers are de-initialized
|
||||
* - ERROR I2C registers are not de-initialized
|
||||
*/
|
||||
uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check the I2C Instance I2Cx */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
|
||||
|
||||
if (I2Cx == I2C1)
|
||||
{
|
||||
/* Force reset of I2C clock */
|
||||
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
|
||||
|
||||
/* Release reset of I2C clock */
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
|
||||
}
|
||||
else if (I2Cx == I2C2)
|
||||
{
|
||||
/* Force reset of I2C clock */
|
||||
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
|
||||
|
||||
/* Release reset of I2C clock */
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
|
||||
|
||||
}
|
||||
#if defined(I2C3)
|
||||
else if (I2Cx == I2C3)
|
||||
{
|
||||
/* Force reset of I2C clock */
|
||||
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3);
|
||||
|
||||
/* Release reset of I2C clock */
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
|
||||
}
|
||||
#endif
|
||||
else
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
|
||||
* @param I2Cx I2C Instance.
|
||||
* @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS I2C registers are initialized
|
||||
* - ERROR Not applicable
|
||||
*/
|
||||
uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
|
||||
{
|
||||
LL_RCC_ClocksTypeDef rcc_clocks;
|
||||
|
||||
/* Check the I2C Instance I2Cx */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
|
||||
|
||||
/* Check the I2C parameters from I2C_InitStruct */
|
||||
assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
|
||||
assert_param(IS_LL_I2C_CLOCK_SPEED(I2C_InitStruct->ClockSpeed));
|
||||
assert_param(IS_LL_I2C_DUTY_CYCLE(I2C_InitStruct->DutyCycle));
|
||||
#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
|
||||
assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
|
||||
assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
|
||||
#endif
|
||||
assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
|
||||
assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
|
||||
assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
|
||||
|
||||
/* Disable the selected I2Cx Peripheral */
|
||||
LL_I2C_Disable(I2Cx);
|
||||
|
||||
/* Retrieve Clock frequencies */
|
||||
LL_RCC_GetSystemClocksFreq(&rcc_clocks);
|
||||
|
||||
#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
|
||||
/*---------------------------- I2Cx FLTR Configuration -----------------------
|
||||
* Configure the analog and digital noise filters with parameters :
|
||||
* - AnalogFilter: I2C_FLTR_ANFOFF bit
|
||||
* - DigitalFilter: I2C_FLTR_DNF[3:0] bits
|
||||
*/
|
||||
LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
|
||||
|
||||
#endif
|
||||
/*---------------------------- I2Cx SCL Clock Speed Configuration ------------
|
||||
* Configure the SCL speed :
|
||||
* - ClockSpeed: I2C_CR2_FREQ[5:0], I2C_TRISE_TRISE[5:0], I2C_CCR_FS,
|
||||
* and I2C_CCR_CCR[11:0] bits
|
||||
* - DutyCycle: I2C_CCR_DUTY[7:0] bits
|
||||
*/
|
||||
LL_I2C_ConfigSpeed(I2Cx, rcc_clocks.PCLK1_Frequency, I2C_InitStruct->ClockSpeed, I2C_InitStruct->DutyCycle);
|
||||
|
||||
/*---------------------------- I2Cx OAR1 Configuration -----------------------
|
||||
* Disable, Configure and Enable I2Cx device own address 1 with parameters :
|
||||
* - OwnAddress1: I2C_OAR1_ADD[9:8], I2C_OAR1_ADD[7:1] and I2C_OAR1_ADD0 bits
|
||||
* - OwnAddrSize: I2C_OAR1_ADDMODE bit
|
||||
*/
|
||||
LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
|
||||
|
||||
/*---------------------------- I2Cx MODE Configuration -----------------------
|
||||
* Configure I2Cx peripheral mode with parameter :
|
||||
* - PeripheralMode: I2C_CR1_SMBUS, I2C_CR1_SMBTYPE and I2C_CR1_ENARP bits
|
||||
*/
|
||||
LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
|
||||
|
||||
/* Enable the selected I2Cx Peripheral */
|
||||
LL_I2C_Enable(I2Cx);
|
||||
|
||||
/*---------------------------- I2Cx CR2 Configuration ------------------------
|
||||
* Configure the ACKnowledge or Non ACKnowledge condition
|
||||
* after the address receive match code or next received byte with parameter :
|
||||
* - TypeAcknowledge: I2C_CR2_NACK bit
|
||||
*/
|
||||
LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_I2C_InitTypeDef field to default value.
|
||||
* @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
|
||||
{
|
||||
/* Set I2C_InitStruct fields to default values */
|
||||
I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C;
|
||||
I2C_InitStruct->ClockSpeed = 5000U;
|
||||
I2C_InitStruct->DutyCycle = LL_I2C_DUTYCYCLE_2;
|
||||
#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
|
||||
I2C_InitStruct->AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE;
|
||||
I2C_InitStruct->DigitalFilter = 0U;
|
||||
#endif
|
||||
I2C_InitStruct->OwnAddress1 = 0U;
|
||||
I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
|
||||
I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* I2C1 || I2C2 || I2C3 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
1679
cubemx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rcc.c
Normal file
1679
cubemx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rcc.c
Normal file
File diff suppressed because it is too large
Load Diff
749
cubemx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_utils.c
Normal file
749
cubemx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_utils.c
Normal file
@@ -0,0 +1,749 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_ll_utils.c
|
||||
* @author MCD Application Team
|
||||
* @brief UTILS LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_ll_utils.h"
|
||||
#include "stm32f4xx_ll_rcc.h"
|
||||
#include "stm32f4xx_ll_system.h"
|
||||
#include "stm32f4xx_ll_pwr.h"
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
/** @addtogroup STM32F4xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup UTILS_LL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @addtogroup UTILS_LL_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
#if defined(RCC_MAX_FREQUENCY_SCALE1)
|
||||
#define UTILS_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
|
||||
#endif /*RCC_MAX_FREQUENCY_SCALE1 */
|
||||
#define UTILS_MAX_FREQUENCY_SCALE2 RCC_MAX_FREQUENCY_SCALE2 /*!< Maximum frequency for system clock at power scale2, in Hz */
|
||||
#if defined(RCC_MAX_FREQUENCY_SCALE3)
|
||||
#define UTILS_MAX_FREQUENCY_SCALE3 RCC_MAX_FREQUENCY_SCALE3 /*!< Maximum frequency for system clock at power scale3, in Hz */
|
||||
#endif /* MAX_FREQUENCY_SCALE3 */
|
||||
|
||||
/* Defines used for PLL range */
|
||||
#define UTILS_PLLVCO_INPUT_MIN RCC_PLLVCO_INPUT_MIN /*!< Frequency min for PLLVCO input, in Hz */
|
||||
#define UTILS_PLLVCO_INPUT_MAX RCC_PLLVCO_INPUT_MAX /*!< Frequency max for PLLVCO input, in Hz */
|
||||
#define UTILS_PLLVCO_OUTPUT_MIN RCC_PLLVCO_OUTPUT_MIN /*!< Frequency min for PLLVCO output, in Hz */
|
||||
#define UTILS_PLLVCO_OUTPUT_MAX RCC_PLLVCO_OUTPUT_MAX /*!< Frequency max for PLLVCO output, in Hz */
|
||||
|
||||
/* Defines used for HSE range */
|
||||
#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
|
||||
#define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz */
|
||||
|
||||
/* Defines used for FLASH latency according to HCLK Frequency */
|
||||
#if defined(FLASH_SCALE1_LATENCY1_FREQ)
|
||||
#define UTILS_SCALE1_LATENCY1_FREQ FLASH_SCALE1_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
|
||||
#endif
|
||||
#if defined(FLASH_SCALE1_LATENCY2_FREQ)
|
||||
#define UTILS_SCALE1_LATENCY2_FREQ FLASH_SCALE1_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
|
||||
#endif
|
||||
#if defined(FLASH_SCALE1_LATENCY3_FREQ)
|
||||
#define UTILS_SCALE1_LATENCY3_FREQ FLASH_SCALE1_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
|
||||
#endif
|
||||
#if defined(FLASH_SCALE1_LATENCY4_FREQ)
|
||||
#define UTILS_SCALE1_LATENCY4_FREQ FLASH_SCALE1_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
|
||||
#endif
|
||||
#if defined(FLASH_SCALE1_LATENCY5_FREQ)
|
||||
#define UTILS_SCALE1_LATENCY5_FREQ FLASH_SCALE1_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
|
||||
#endif
|
||||
#define UTILS_SCALE2_LATENCY1_FREQ FLASH_SCALE2_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
|
||||
#define UTILS_SCALE2_LATENCY2_FREQ FLASH_SCALE2_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
|
||||
#if defined(FLASH_SCALE2_LATENCY3_FREQ)
|
||||
#define UTILS_SCALE2_LATENCY3_FREQ FLASH_SCALE2_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
|
||||
#endif
|
||||
#if defined(FLASH_SCALE2_LATENCY4_FREQ)
|
||||
#define UTILS_SCALE2_LATENCY4_FREQ FLASH_SCALE2_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
|
||||
#endif
|
||||
#if defined(FLASH_SCALE2_LATENCY5_FREQ)
|
||||
#define UTILS_SCALE2_LATENCY5_FREQ FLASH_SCALE2_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
|
||||
#endif
|
||||
#if defined(FLASH_SCALE3_LATENCY1_FREQ)
|
||||
#define UTILS_SCALE3_LATENCY1_FREQ FLASH_SCALE3_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
|
||||
#endif
|
||||
#if defined(FLASH_SCALE3_LATENCY2_FREQ)
|
||||
#define UTILS_SCALE3_LATENCY2_FREQ FLASH_SCALE3_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
|
||||
#endif
|
||||
#if defined(FLASH_SCALE3_LATENCY3_FREQ)
|
||||
#define UTILS_SCALE3_LATENCY3_FREQ FLASH_SCALE3_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
|
||||
#endif
|
||||
#if defined(FLASH_SCALE3_LATENCY4_FREQ)
|
||||
#define UTILS_SCALE3_LATENCY4_FREQ FLASH_SCALE3_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */
|
||||
#endif
|
||||
#if defined(FLASH_SCALE3_LATENCY5_FREQ)
|
||||
#define UTILS_SCALE3_LATENCY5_FREQ FLASH_SCALE3_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 3 */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup UTILS_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
|
||||
|
||||
#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
|
||||
|| ((__VALUE__) == LL_RCC_APB1_DIV_2) \
|
||||
|| ((__VALUE__) == LL_RCC_APB1_DIV_4) \
|
||||
|| ((__VALUE__) == LL_RCC_APB1_DIV_8) \
|
||||
|| ((__VALUE__) == LL_RCC_APB1_DIV_16))
|
||||
|
||||
#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
|
||||
|| ((__VALUE__) == LL_RCC_APB2_DIV_2) \
|
||||
|| ((__VALUE__) == LL_RCC_APB2_DIV_4) \
|
||||
|| ((__VALUE__) == LL_RCC_APB2_DIV_8) \
|
||||
|| ((__VALUE__) == LL_RCC_APB2_DIV_16))
|
||||
|
||||
#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_8) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_9) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_16) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_17) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_18) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_19) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_20) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_21) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_22) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_23) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_24) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_25) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_26) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_27) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_28) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_29) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_30) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_31) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_32) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_33) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_34) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_35) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_36) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_37) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_38) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_39) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_40) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_41) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_42) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_43) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_44) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_45) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_46) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_47) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_48) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_49) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_50) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_51) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_52) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_53) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_54) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_55) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_56) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_57) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_58) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_59) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_60) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_61) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_62) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLM_DIV_63))
|
||||
|
||||
#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((RCC_PLLN_MIN_VALUE <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLN_MAX_VALUE))
|
||||
|
||||
#define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLP_DIV_4) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLP_DIV_6) \
|
||||
|| ((__VALUE__) == LL_RCC_PLLP_DIV_8))
|
||||
|
||||
#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
|
||||
|
||||
#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
|
||||
|
||||
#if !defined(RCC_MAX_FREQUENCY_SCALE1)
|
||||
#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
|
||||
((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
|
||||
|
||||
#elif defined(RCC_MAX_FREQUENCY_SCALE3)
|
||||
#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
|
||||
(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
|
||||
((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
|
||||
|
||||
#else
|
||||
#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
|
||||
((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))
|
||||
|
||||
#endif /* RCC_MAX_FREQUENCY_SCALE1*/
|
||||
#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
|
||||
|| ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
|
||||
|
||||
#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
|
||||
* @{
|
||||
*/
|
||||
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
|
||||
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
|
||||
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
static ErrorStatus UTILS_PLL_IsBusy(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup UTILS_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup UTILS_LL_EF_DELAY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function configures the Cortex-M SysTick source to have 1ms time base.
|
||||
* @note When a RTOS is used, it is recommended to avoid changing the Systick
|
||||
* configuration by calling this function, for a delay use rather osDelay RTOS service.
|
||||
* @param HCLKFrequency HCLK frequency in Hz
|
||||
* @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
|
||||
* @retval None
|
||||
*/
|
||||
void LL_Init1msTick(uint32_t HCLKFrequency)
|
||||
{
|
||||
/* Use frequency provided in argument */
|
||||
LL_InitTick(HCLKFrequency, 1000U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function provides accurate delay (in milliseconds) based
|
||||
* on SysTick counter flag
|
||||
* @note When a RTOS is used, it is recommended to avoid using blocking delay
|
||||
* and use rather osDelay service.
|
||||
* @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
|
||||
* will configure Systick to 1ms
|
||||
* @param Delay specifies the delay time length, in milliseconds.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_mDelay(uint32_t Delay)
|
||||
{
|
||||
__IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
|
||||
/* Add this code to indicate that local variable is not used */
|
||||
((void)tmp);
|
||||
|
||||
/* Add a period to guaranty minimum wait */
|
||||
if(Delay < LL_MAX_DELAY)
|
||||
{
|
||||
Delay++;
|
||||
}
|
||||
|
||||
while (Delay)
|
||||
{
|
||||
if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
|
||||
{
|
||||
Delay--;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UTILS_EF_SYSTEM
|
||||
* @brief System Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### System Configuration functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
System, AHB and APB buses clocks configuration
|
||||
|
||||
(+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 180000000 Hz.
|
||||
@endverbatim
|
||||
@internal
|
||||
Depending on the device voltage range, the maximum frequency should be
|
||||
adapted accordingly to the Refenece manual.
|
||||
@endinternal
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function sets directly SystemCoreClock CMSIS variable.
|
||||
* @note Variable can be calculated also through SystemCoreClockUpdate function.
|
||||
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
|
||||
* @retval None
|
||||
*/
|
||||
void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
|
||||
{
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock = HCLKFrequency;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update number of Flash wait states in line with new frequency and current
|
||||
voltage range.
|
||||
* @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V
|
||||
* @param HCLK_Frequency HCLK frequency
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: Latency has been modified
|
||||
* - ERROR: Latency cannot be modified
|
||||
*/
|
||||
ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
|
||||
{
|
||||
uint32_t timeout;
|
||||
uint32_t getlatency;
|
||||
uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
|
||||
/* Frequency cannot be equal to 0 */
|
||||
if(HCLK_Frequency == 0U)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
|
||||
{
|
||||
#if defined (UTILS_SCALE1_LATENCY5_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_5;
|
||||
}
|
||||
#endif /*UTILS_SCALE1_LATENCY5_FREQ */
|
||||
#if defined (UTILS_SCALE1_LATENCY4_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_4;
|
||||
}
|
||||
#endif /* UTILS_SCALE1_LATENCY4_FREQ */
|
||||
#if defined (UTILS_SCALE1_LATENCY3_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_3;
|
||||
}
|
||||
#endif /* UTILS_SCALE1_LATENCY3_FREQ */
|
||||
#if defined (UTILS_SCALE1_LATENCY2_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_2;
|
||||
}
|
||||
else
|
||||
{
|
||||
if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_1;
|
||||
}
|
||||
}
|
||||
#endif /* UTILS_SCALE1_LATENCY2_FREQ */
|
||||
}
|
||||
if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
|
||||
{
|
||||
#if defined (UTILS_SCALE2_LATENCY5_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_5;
|
||||
}
|
||||
#endif /*UTILS_SCALE1_LATENCY5_FREQ */
|
||||
#if defined (UTILS_SCALE2_LATENCY4_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_4;
|
||||
}
|
||||
#endif /*UTILS_SCALE1_LATENCY4_FREQ */
|
||||
#if defined (UTILS_SCALE2_LATENCY3_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_3;
|
||||
}
|
||||
#endif /*UTILS_SCALE1_LATENCY3_FREQ */
|
||||
if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_2;
|
||||
}
|
||||
else
|
||||
{
|
||||
if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_1;
|
||||
}
|
||||
}
|
||||
}
|
||||
#if defined (LL_PWR_REGU_VOLTAGE_SCALE3)
|
||||
if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE3)
|
||||
{
|
||||
#if defined (UTILS_SCALE3_LATENCY3_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_3;
|
||||
}
|
||||
#endif /*UTILS_SCALE1_LATENCY3_FREQ */
|
||||
#if defined (UTILS_SCALE3_LATENCY2_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_2;
|
||||
}
|
||||
else
|
||||
{
|
||||
if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_1;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /*UTILS_SCALE1_LATENCY2_FREQ */
|
||||
#endif /* LL_PWR_REGU_VOLTAGE_SCALE3 */
|
||||
|
||||
LL_FLASH_SetLatency(latency);
|
||||
/* Check that the new number of wait states is taken into account to access the Flash
|
||||
memory by reading the FLASH_ACR register */
|
||||
timeout = 2;
|
||||
do
|
||||
{
|
||||
/* Wait for Flash latency to be updated */
|
||||
getlatency = LL_FLASH_GetLatency();
|
||||
timeout--;
|
||||
} while ((getlatency != latency) && (timeout > 0));
|
||||
|
||||
if(getlatency != latency)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = SUCCESS;
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
|
||||
* @note The application need to ensure that PLL is disabled.
|
||||
* @note Function is based on the following formula:
|
||||
* - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
|
||||
* - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)
|
||||
* - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)
|
||||
* - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)
|
||||
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
|
||||
* the configuration information for the PLL.
|
||||
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
|
||||
* the configuration information for the BUS prescalers.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: Max frequency configuration done
|
||||
* - ERROR: Max frequency configuration not done
|
||||
*/
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
|
||||
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
uint32_t pllfreq = 0U;
|
||||
|
||||
/* Check if one of the PLL is enabled */
|
||||
if(UTILS_PLL_IsBusy() == SUCCESS)
|
||||
{
|
||||
/* Calculate the new PLL output frequency */
|
||||
pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
|
||||
|
||||
/* Enable HSI if not enabled */
|
||||
if(LL_RCC_HSI_IsReady() != 1U)
|
||||
{
|
||||
LL_RCC_HSI_Enable();
|
||||
while (LL_RCC_HSI_IsReady() != 1U)
|
||||
{
|
||||
/* Wait for HSI ready */
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure PLL */
|
||||
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
|
||||
UTILS_PLLInitStruct->PLLP);
|
||||
|
||||
/* Enable PLL and switch system clock to PLL */
|
||||
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Current PLL configuration cannot be modified */
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function configures system clock with HSE as clock source of the PLL
|
||||
* @note The application need to ensure that PLL is disabled.
|
||||
* - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
|
||||
* - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)
|
||||
* - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)
|
||||
* - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)
|
||||
* @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000
|
||||
* @param HSEBypass This parameter can be one of the following values:
|
||||
* @arg @ref LL_UTILS_HSEBYPASS_ON
|
||||
* @arg @ref LL_UTILS_HSEBYPASS_OFF
|
||||
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
|
||||
* the configuration information for the PLL.
|
||||
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
|
||||
* the configuration information for the BUS prescalers.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: Max frequency configuration done
|
||||
* - ERROR: Max frequency configuration not done
|
||||
*/
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
|
||||
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
uint32_t pllfreq = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
|
||||
assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
|
||||
|
||||
/* Check if one of the PLL is enabled */
|
||||
if(UTILS_PLL_IsBusy() == SUCCESS)
|
||||
{
|
||||
/* Calculate the new PLL output frequency */
|
||||
pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
|
||||
|
||||
/* Enable HSE if not enabled */
|
||||
if(LL_RCC_HSE_IsReady() != 1U)
|
||||
{
|
||||
/* Check if need to enable HSE bypass feature or not */
|
||||
if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
|
||||
{
|
||||
LL_RCC_HSE_EnableBypass();
|
||||
}
|
||||
else
|
||||
{
|
||||
LL_RCC_HSE_DisableBypass();
|
||||
}
|
||||
|
||||
/* Enable HSE */
|
||||
LL_RCC_HSE_Enable();
|
||||
while (LL_RCC_HSE_IsReady() != 1U)
|
||||
{
|
||||
/* Wait for HSE ready */
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure PLL */
|
||||
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
|
||||
UTILS_PLLInitStruct->PLLP);
|
||||
|
||||
/* Enable PLL and switch system clock to PLL */
|
||||
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Current PLL configuration cannot be modified */
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UTILS_LL_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Function to check that PLL can be modified
|
||||
* @param PLL_InputFrequency PLL input frequency (in Hz)
|
||||
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
|
||||
* the configuration information for the PLL.
|
||||
* @retval PLL output frequency (in Hz)
|
||||
*/
|
||||
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
|
||||
{
|
||||
uint32_t pllfreq = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
|
||||
assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
|
||||
assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
|
||||
|
||||
/* Check different PLL parameters according to RM */
|
||||
/* - PLLM: ensure that the VCO input frequency ranges from @ref UTILS_PLLVCO_INPUT_MIN to @ref UTILS_PLLVCO_INPUT_MAX MHz. */
|
||||
pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos));
|
||||
assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
|
||||
|
||||
/* - PLLN: ensure that the VCO output frequency is between @ref UTILS_PLLVCO_OUTPUT_MIN and @ref UTILS_PLLVCO_OUTPUT_MAX .*/
|
||||
pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
|
||||
assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
|
||||
|
||||
/* - PLLP: ensure that max frequency at @ref RCC_MAX_FREQUENCY Hz is reached */
|
||||
pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
|
||||
assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
|
||||
|
||||
return pllfreq;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function to check that PLL can be modified
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: PLL modification can be done
|
||||
* - ERROR: PLL is busy
|
||||
*/
|
||||
static ErrorStatus UTILS_PLL_IsBusy(void)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check if PLL is busy*/
|
||||
if(LL_RCC_PLL_IsReady() != 0U)
|
||||
{
|
||||
/* PLL configuration cannot be modified */
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
#if defined(RCC_PLLSAI_SUPPORT)
|
||||
/* Check if PLLSAI is busy*/
|
||||
if(LL_RCC_PLLSAI_IsReady() != 0U)
|
||||
{
|
||||
/* PLLSAI1 configuration cannot be modified */
|
||||
status = ERROR;
|
||||
}
|
||||
#endif /*RCC_PLLSAI_SUPPORT*/
|
||||
#if defined(RCC_PLLI2S_SUPPORT)
|
||||
/* Check if PLLI2S is busy*/
|
||||
if(LL_RCC_PLLI2S_IsReady() != 0U)
|
||||
{
|
||||
/* PLLI2S configuration cannot be modified */
|
||||
status = ERROR;
|
||||
}
|
||||
#endif /*RCC_PLLI2S_SUPPORT*/
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function to enable PLL and switch system clock to PLL
|
||||
* @param SYSCLK_Frequency SYSCLK frequency
|
||||
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
|
||||
* the configuration information for the BUS prescalers.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: No problem to switch system to PLL
|
||||
* - ERROR: Problem to switch system to PLL
|
||||
*/
|
||||
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
uint32_t hclk_frequency = 0U;
|
||||
|
||||
assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
|
||||
assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
|
||||
assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
|
||||
|
||||
/* Calculate HCLK frequency */
|
||||
hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
|
||||
|
||||
/* Increasing the number of wait states because of higher CPU frequency */
|
||||
if(SystemCoreClock < hclk_frequency)
|
||||
{
|
||||
/* Set FLASH latency to highest latency */
|
||||
status = LL_SetFlashLatency(hclk_frequency);
|
||||
}
|
||||
|
||||
/* Update system clock configuration */
|
||||
if(status == SUCCESS)
|
||||
{
|
||||
/* Enable PLL */
|
||||
LL_RCC_PLL_Enable();
|
||||
while (LL_RCC_PLL_IsReady() != 1U)
|
||||
{
|
||||
/* Wait for PLL ready */
|
||||
}
|
||||
|
||||
/* Sysclk activation on the main PLL */
|
||||
LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
|
||||
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
|
||||
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
|
||||
{
|
||||
/* Wait for system clock switch to PLL */
|
||||
}
|
||||
|
||||
/* Set APB1 & APB2 prescaler*/
|
||||
LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
|
||||
LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
|
||||
}
|
||||
|
||||
/* Decreasing the number of wait states because of lower CPU frequency */
|
||||
if(SystemCoreClock > hclk_frequency)
|
||||
{
|
||||
/* Set FLASH latency to lowest latency */
|
||||
status = LL_SetFlashLatency(hclk_frequency);
|
||||
}
|
||||
|
||||
/* Update SystemCoreClock variable */
|
||||
if(status == SUCCESS)
|
||||
{
|
||||
LL_SetSystemCoreClock(hclk_frequency);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -135,7 +135,7 @@ ProjectManager.ToolChainLocation=
|
||||
ProjectManager.UAScriptAfterPath=
|
||||
ProjectManager.UAScriptBeforePath=
|
||||
ProjectManager.UnderRoot=false
|
||||
ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-false,3-MX_I2C1_Init-I2C1-false-HAL-false,4-MX_USART2_UART_Init-USART2-false-HAL-false
|
||||
ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-false,3-MX_I2C1_Init-I2C1-false-LL-false,4-MX_USART2_UART_Init-USART2-false-HAL-false
|
||||
RCC.48MHZClocksFreq_Value=50000000
|
||||
RCC.AHBFreq_Value=100000000
|
||||
RCC.APB1CLKDivider=RCC_HCLK_DIV2
|
||||
|
||||
Reference in New Issue
Block a user